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Motorola Grows GaAs on Silicon

Photonics Spectra
Oct 2001
Daniel S. Burgess

TEMPE, Ariz. -- While III-V semiconductors have revolutionized electronics and photonics, the expense of their manufacture has limited widespread application. Researchers at Motorola Labs promise this will change. They have learned how to grow gallium arsenide on silicon substrates, enabling the production of GaAs wafers twice as large as today's, and they hope to do the same with indium phosphide and gallium nitride.

techGrows

Jamal Ramdani (left) and Ravi Droopad of Motorola Labs display a 12-in. wafer of gallium arsenide on silicon. The wafer incorporates an interlayer of strontium titanate to mitigate lattice mismatch. Courtesy of Motorola.

The achievement is attributable to a combination of know-how and serendipity. William J. Ooms, director of materials device and energy research at Motorola and project manager for the work, noted that the scientists had been researching the use of strontium titanate with silicon since 1995, hoping to develop thinner gate insulators for silicon CMOS circuitry. They found that the addition of oxygen to the deposition chamber led to the formation of an amorphous interlayer between the STO and silicon, which would seem to create leakage problems for the gates. Principal staff scientist Jamal Ramdani, however, saw an opportunity.

Ramdani, with Lyndee Hilt and Ravi Droopad, who performed the initial investigations into STO and silicon, determined that the interlayer eases the lattice mismatch between the materials, enabling the growth of a robust layer of STO on the substrate. This is key, because STO and GaAs have a lattice mismatch of only approximately 2 percent, which tolerates the growth of 80- to 100-A-thick layers without dislocations, Ooms said. (In contrast, GaAs and silicon have a lattice mismatch of 4.1 percent, foreclosing the possibility of growing GaAs directly on silicon.)

Moreover, Ooms noted, the different thermal expansion coefficients of GaAs and silicon strain a cooling wafer, which can cause bowing or cracking. The amorphous interlayer, however, eases this strain and has enabled the researchers to produce 12-in., flat GaAs-on-silicon wafers in commercial-grade molecular-beam-epitaxy equipment from IQE plc of Bethlehem, Pa.

The ability to grow GaAs on silicon should reduce the price of GaAs wafers and, therefore, of high-performance semiconductor devices. Currently, manufacturers grow GaAs on GaAs substrates, a process that limits the size of the wafers to 6 in. If the history of silicon is any guide, scaling up the size of the wafers --and the number of components that can be produced per wafer -- will lead to an exponential drop in cost.

In the mid- and long term, Ooms said, the process will open the door to integrating currently discrete components. By growing GaAs on particular areas of silicon CMOS circuitry, which the team has demonstrated by producing a power amplifier for a cellular phone, manufacturers can reduce part counts and, thus, assembly costs. Eventually, he said, the technique may enable on-chip and chip-to-chip optical interconnects that could avoid the losses in speed that come from running signals off-chip through wires.

Motorola will license the growth process to the industry, and Ooms expects to see 6-in. GaAs-on-silicon wafers in full production in 2003. Other, optically interesting compound semiconductors such as InP and GaN will require different materials to act as the interface layer with the silicon, and fundamental research into the problem is ongoing.

"This is as exciting as when we started putting multiple transistors on an integrated circuit," Ooms said. "The ability to combine compound semiconductors with silicon CMOS will radically alter the way we make electronics."


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