Tech workshop focuses on PIC packaging
Packaging for photonic integrated circuits continues to evolve, despite challenges. For silicon photonics, some of the potential solutions include wafer-level methods and “microbench” technologies for multichip device packaging. Since photonics does not yet have the volume to drive the need for cost-effective packages, it is possible that a drive for nonhermetic approaches may be one of the better solutions. That was the audience consensus at the EPIC technology workshop on Photonic Integrated Circuits Packaging Standardization, hosted in June at the TE Connectivity facility in ‘s-Hertogenbosch, the Netherlands.
The two-day event had 56 attendees, limited to one representative per company, and opened with a brief introduction to PIC packaging standards by Carlos Lee, director general of EPIC, the European Photonics Industry Consortium.
Packaging costs are likely to become the main reason for the slow uptake of photonic devices, and equipment development has been hampered by this, the group found. Industry standards have long been useful for electronics manufacturing; now that some optics-packaging automation equipment has pick-and-place capability with submicron mechanics and active optical alignment, the workshop attendees agreed that designers of photonic devices need a set of “design rules” to allow devices to work with machine capabilities.
Companies often develop internal standards, but these frequently do not translate to those of outside vendors. Also, many companies are still using older machinery because lack of market growth prevents investment in newer capabilities. This can hinder product evolution, the attendees said, and they agreed that working with an organization such as EPIC would be a better way to create default standards for PIC packages.
In interfacing optical links, cost is one challenge: The lack of standard options means that component assembly accounts for 30 to 50 percent of the cost. This part of the discussion led some members of the audience to propose not integrating, due to thermal issues, by keeping optical and electrical parts separately packaged. That debate led to a discussion of integrating more on-chip as a way to reduce package costs.
Images courtesy of EPIC.
One solution discussed was the possibility of using large-scale, high-volume processes for wafer-level packaging of photonic components. The discussion that followed indicated that the photonics community should consider using available semiconductor package capabilities.
To take advantage of electronic design automation software platforms in all stages of the design and manufacturing process using “standardized” process design kits or other tools, standards should be set for die sizes, packages, optical, and DC and radio-frequency port locations, as well as radio-frequency connections on and off the chip. The workshop attendees suggested that EPIC should encourage members to adopt process design kits by publicizing what is available and where the kits can be obtained.
Regarding testing of packages for reliability and other factors, the group found that the conditions for testing need to be defined and standardized because, due to evolving developments, the long-term reliability requirement is coming down from 25 to five years.
The group ultimately concluded that:
• EPIC should create a “library” of the typical standards for PIC packaging that should be utilized and become a reference for the industry.
• EPIC should survey its membership to see what the commonality is for photonic components, what the envisaged market sizes are, and what standards companies consider to be necessary.
The final session of the workshop looked at some key photonics packaging projects now under way: the PARADIGM project, the PhoxTroT project, and the EU Framework 7 program PHASTFLEX (Photonic Hybrid Assembly Through Flexible Waveguides).
Workshop presentations available
For more information about the workshop, or to request copies of the presentations, contact Carlos Lee of EPIC at email@example.com.
Here are the presentations that were given:
Bob Musk, Entroptix: History of photonic packages.
Ignazio Piacentini, PI miCos: Packaging automation.
Andy Longford, PandA Europe: Standards in the electronics industry.
Mike Wale, Oclaro: Optoelectronic integration from the packaging perspective.
Bert Offrein, IBM Research: Challenges for interfacing optical links.
Michael Lebby, OneChip Photonics: Integrating on-chip to reduce package costs.
Timo Aalto, VTT: Packaging options.
Jeroen Duis, TE Connectivity: Review of standards.
Ronald Dekker, XiO Photonics: Challenges of small-mode-field diameters (SMD) optical parts.
Markus Riester, Multiphoton Optics: 3-D laser technology for packaging.
Dario Lo Cascio, Technobis ipps: Developments in packaging.
Steffen Kröhnert, Nanium: High-volume processes for wafer-level packaging.
Christian Koos, KIT: Wire-bond semiconductor assembly process.
Twan Korthorst, PhoeniX Software: Electronic design automation software platforms for design and manufacturing.
Nicola Pavarelli, Tyndall: Design rules for low-cost package solutions.
Stéphane Bernabe, CEA-LETI: Semiconductor-type packaging options.
Torsten Vahrenkamp, ficonTEC: Packaging with active and passive alignment.
Bob Musk on behalf of Gooch & Housego: The PARADIGM project.
Richard Pitwon, Seagate (Xyratex): The PhoxTroT and HDPUG projects.
Arne Leinse, LioniX: The EU Framework 7 program PHASTFLEX.
- A cross-sectional slice cut from an ingot of either single-crystal, fused, polycrystalline or amorphous material that has refined surfaces either lapped or polished. Wafers are used either as substrates for electronic device manufacturing or as optics. Typically, they are made of silicon, quartz, gallium arsenide or indium phosphide.
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