Two-Photon Process Probes Circuits
Sometimes two photons are better than one. A new two-photon-absorption technique developed at the US Naval Research Laboratory in Washington for testing the radiation sensitivity of semiconductors could lead to more robust integrated circuits for space- based applications and for advanced earthbound devices.
A new two-photon absorption technique enables users to investigate the effects of radiation on electronic devices by controllably inducing errors into a circuit. An electron-hole density plot as a function of depth for 1-nJ, 120-fs pulses of 1.26-µm radiation in silicon illustrates that the carriers generated in the process are concentrated near the laser's focus w(z).
When an energetic particle or a photon punches through a circuit, it leaves a highly localized charge track that can produce single-event effects: random glitches such as lost data, faulty results or device failure. Because integrated circuits are packaged in opaque materials, these effects are most likely to occur in environments, such as space, that are dense with energetic particles. As circuits shrink, however, the issue could be of more concern for devices in terrestrial or avionic applications.
Conventional laser-based techniques inject individual photons of the proper energy to be absorbed by and to induce defects in the semiconductor under test. The new technique, in contrast, employs photons whose energy is too low to cause single-event effects on their own. Charge deposition occurs only when two or more photons interact within a photon-dense focal region, enabling the user to create defects at particular depths and thereby map the sensitivity in three dimensions.
In a proof-of-principle demonstration that compared single-event transients induced in the nodes of a voltage comparator and an operational amplifier, the researchers found that a 1.26-µm Ti:sapphire-pumped optical parametric amplifier in the two-photon-absorption configuration yielded equivalent results to a 590-nm laser in the single-photon technique. They also investigated the three-dimensional mapping ability of the new technique by probing below a transistor's surface, thus creating a depth-related profile of the device sensitivity that would otherwise be impossible to obtain.
"The most significant advantage of this approach is the ability to interrogate the devices from the back side through the wafer," said Dale McMorrow of the research lab. "This will permit us to evaluate devices that ... cannot be tested using conventional techniques." Research into the method continues, with investigations under way to detail its 3-D mapping ability and its potential for back-side illumination.
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