Tiny Measurements Present Big Challenges
In semiconductor manufacturing, photonics is used not only for imaging circuit layers, but also for measuring the size and location of patterned features. The question is, will photonic techniques be able to handle those metrology needs as feature sizes shrink from today's 100-nm state-of-the-art to the 45- and 32-nm nodes that will replace them in five years or so? That was the subject of two papers presented in February at the SPIE Microlithography 2004 conference held deep within Silicon Valley in Santa Clara, Calif.
Intel Corp. produced test wafers with hole and line sizes similar to those that future processes may fabricate to determine if current metrology techniques can handle the required measurement tasks. Courtesy of Intel.
One paper examined the ability of different measurement techniques to accurately gauge critical dimensions. Bryan J. Rice, extreme-UV lithography engineer at Intel Corp. in Santa Clara and lead author of the paper, summed up scatterometry's performance: "It is capable, but there are areas where it needs some improvement." In the study, he and the other researchers from Intel and from Lawrence Berkeley National Laboratory in California used e-beam lithography to create test wafers with lines, spaces and holes that reflect those smaller feature sizes.
Despite its name, the smallest features at the 32-nm node will be isolated lines that are 10 to 15 nm in width. Holes, which provide connectivity paths through insulating layers, will be 35 nm in diameter and will have an aspect ratio, depth to width, of approximately 10:1.
The researchers shipped the test wafers to metrology suppliers to see how well various methods could handle the measurement tasks. The techniques tested included scatterometry, conventional scanning electron microscopy (SEM), atomic force microscopy (AFM), and dual-beam and high-energy SEM. Of these, scatterometry and conventional SEM are widely used today for critical dimension measurements.
The results, Rice said, show that AFM won't be up to the challenge without a breakthrough in tip design. High-voltage SEM failed because it damaged transistors. Dual-beam SEM looks promising, but it also will require significant improvement. Both scatterometry and conventional SEM appear to be up to the job but will need refinement.
Scatterometry works by constructing a diffraction grating of lines and spaces on a wafer. Sweeping the wavelength of an interrogating beam from red to ultraviolet produces scattered spectra characteristic of the grating. From this linewidth and feature profile, information can be extracted.
The problem, which will grow more acute as the feature sizes shrink, is that the strength of the scattered signal is proportional to the feature volume. As the signal gets smaller, it becomes more difficult to distinguish between variations in linewidth -- or critical dimensions -- and variations of feature profile, such as sidewall angle.
"I think the biggest challenge," Rice said, "is how to improve signal strength as the overall volume of [critical dimensions] features gets smaller." He noted that simply boosting the power of the incoming beam won't help because scatterometry is a diffraction technique. Nor will packing the features closer together solve the problem, because the feature height also would shrink.
Harry J. Levinson, manager of strategic lithography technology at Advanced Micro Devices Inc. of Sunnyvale, Calif., looked at other metrology requirements, including overlay measurement -- the determination of the amount by which one layer is misaligned to previous ones. The 32-nm node, according to the industry's technology road map, requires overlay to be 2.3 nm. This can be achieved today for 1-µm features using optical methods. He noted that these optical techniques are preferred because they're simpler, cheaper and more reliable.
Where's the catch?
However, there's a catch: 1 µm is much larger than the actual lines and spaces found on a circuit. Levinson said that, because of optical aberrations in the lithography tools, there can be differences in the pattern placement for large features vs. small ones.
One way to address this, he suggests, is to use something akin to the structures that are used in scatterometry. "You have an opportunity to construct your overlay measurement targets from grating structures that represent more of what you have in the circuit," he explained.
He added that this is an active area of research but that no widely accepted solutions have yet emerged. Thus, there's a chance that a nonoptical method eventually will be adopted.
Other feature aspects also are coming to the forefront. One is line edge roughness -- the deviation of an actual feature's edge from the ideal. This, it's widely thought, cannot be measured optically. No one really knows what the specification for such roughness should be, however, so it's possible that an optical method will work.
This is just an example of a trend that affects all semiconductor metrology, whether photonics-based or not: The number of parameters that must be measured increases as the feature size shrinks.
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