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PMC-Sierra Unveils Industry's Highest Performance MIPS Multiprocessor Architecture
Jun 2001
Newstream, June 12 -- PMC-Sierra introduced the architecture for the RM9000x2 integrated multiprocessor, the company's next-generation high-performance MIPS processor designed for the communications market. The RM9000x2 is a scalable multiprocessing architecture that solves the industry-wide problem of slow data transfers between processors in cache coherent systems and offers greater throughput efficiencies over single CPU products. Anchored by dual CPU cores running at 1 GHz, the RM9000x2 achieves maximum performance while drawing only five watts of power.
    Using 0.13-µm high-performance process, the GigaHertz CPU speed and low power is achieved. The twin CPUs connect to high speed memory and I/O interfaces through a multiport, shared memory fabric. High speed I/O connectivity, which includes 500 MHz HyperTransport bus interface, positions the RM9000x2 to target key applications such as core routers, edge routers, remote access products and enterprise servers.
    "Networking is inherently a parallel operation and PMC-Sierra has adapted its microprocessor design to the requirements of high-speed processing within networking equipment," stated Tom Riordan, vice president and general manager of the MIPS Processor Division at PMC-Sierra. "The RM9000x2 architecture is the foundation for future products that will provide greater processing power through additional CPU cores and higher performance I/O interconnect designed for networking equipment."

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