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CEA-Leti and Intel Report on Hybrid Direct-Bonding Self-Assembly Process

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SAN DIEGO, July 6, 2023 — CEA-Leti and Intel have optimized a hybrid direct-bonding, self-assembly process that increases alignment accuracy as well as fabrication throughput by several thousand dies per hour. The approach uses capillary forces of a water droplet to align dies on a target wafer.

Although the microelectronics industry sees the die-to-wafer (D2W) hybrid bonding process as essential for the success of future high-performance computing (HPC) and photonic devices, it’s far more complex than wafer-to-wafer bonding, with lower alignment accuracy and lower die-assembly throughput. CEA-Leti has been developing a self-assembly method for several years, with the goal of substantially increasing throughput and placement accuracy.

“Commercial scale throughput with D2W self-assembly presents two main challenges related to die handling,” said Emilie Bourjot, CEA-Leti’s 3D integration project manager. “If the self-assembly process is combined with a pick-and-place tool, the throughput can be increased by reducing the time of alignment, since the fine alignment is performed by the droplet. When self-assembly is combined with a collective die-handing solution, the throughput is increased by the fact that all dies are bonded together at the same time without any high-precision placement at any time along the process flow.”

Process optimization is another important aspect of the work for increasing process maturity and targeting industrial needs. “With such alignment and throughput performances, it is definitely a promising step allying the magic of physics and a simple drop of water,” Bourjot said.

The paper noted that “capillary forces arise from the principle of surface minimization and are exerted through surface tension in the case of a liquid. From a macroscopic point of view, the liquid tends to minimize its liquid/air interface to reach an equilibrium state with minimized energy.”

“The water dispense technique and the surface preparation to tune the surface hydrophilicity appeared as critical for the proper conduct of the self-assembly process,” the paper stated. “Thus, excellent alignment performance on a homemade collective self-assembly bonding bench was achieved. It resulted in a mean misalignment inferior to 150 nm with a 3σ inferior to 500 nm. Finally, the compatibility of the self-assembly process with a wide range of die dimensions (8 × 8 mm2, 2.7 × 2.7 mm2, 1.3 × 11.8 mm2, and 2.2 × 11.8 mm2) was demonstrated.”

By comparison, state-of-the-art alignment is 1 µm with a pick-and-place tool post-bonding, and the best case is 700 nm, while a self-alignment process offers an alignment below 500 nm and even less than 200 nm, post-bonding.

Explaining the “homemade collective self-assembly bonding bench,” CEA-Leti said, “As no industrial tools for the self-assembly approach exist, the team fabricated its own lab bench enabling a collective self-assembly. The low-reproducibility, manual process control none-the-less achieved alignment of 500 nm and below, which strongly suggests that an industrial tool dedicated to this process would deliver higher reproducibility, robustness, and precision.”

The paper’s conclusion emphasized that despite the progress, “many aspects of the self-assembly still need to be explored and great improvements will only be possible when tool suppliers will develop [an] adapted tool to automate this process.”

For this collaboration, CEA-Leti designed the process flow and performed wafer processing and self-assembly bondings with its expertise in bonding physics, processes, and process integration. It also performed characterizations like nanotopography, scanning acoustic microscopy, and alignment. Intel’s participation included providing specifications, modeling, and pre- and post-bonding process integration expertise to make the self-assembly process foundry compatible.
Jul 2023
1. A localized fracture at the end of a cleaved optical fiber or on a glass surface. 2. An integrated circuit.
A cross-sectional slice cut from an ingot of either single-crystal, fused, polycrystalline or amorphous material that has refined surfaces either lapped or polished. Wafers are used either as substrates for electronic device manufacturing or as optics. Typically, they are made of silicon, quartz, gallium arsenide or indium phosphide.
Businessresearch and Technologyopticschipbondingwaferdie-to-waferD2Wcollaborationresearch and developmentR&DCEA-Letiself-assemblyalignmentfabricationlithographyAmericasIntel

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