Marvell Delivers Advanced Packaging Platform for Custom AI Accelerators
SANTA CLARA, Calif., May 30, 2025 — In a development that it said expands the packaging ecosystem for AI infrastructure, Marvell Technology has introduced a solution that enables multi-chip accelerator designs 2.8x larger than conventional single-die implementations. The multi-die solution, according to Marvell, lowers the total cost of ownership for custom AI accelerator silicon.
According to Marvell, as a manufacturing alternative to traditional interposer-based multi-chip approaches, the solution can enable lower power consumption and increased chiplet yields in addition to more efficient die-to-die interconnect(s) and lower product cost.
Marvell said in a press release that the platform has been qualified with a major hyperscaler and is currently ramping in production.
According to the company, the optimized multi-chip packaging platform was designed with the aim of building a broad technology platform to enable custom XPU design in the future. The Marvell approach integrates 1390 mm2 of silicon and four pieces of high-bandwidth memory 3/3E (HBM3/3E) memory stacks and uses six interposer re-distribution layer (RDL) layers. This, the company said, enables multi-die AI accelerator solutions that are 2.8× larger than the largest possible single-chip design. The Marvell multi-die packaging solution allows for shorter die-to-die interconnects and a modular RDL interposer.
In conventional chiplets, a single interposer will span the floor space of the chips it connects, as well as any area between them. The RDL interposers in the current solution are form-fitted to individual computing dies and connected by high-bandwidth paths. The approach reduces materials while increasing chiplet yields by enabling manufacturers to replace individual dies, according to Marvell. The multi-die packaging platform also enables the integration of passive devices to reduce potential signal noise within the chiplet package caused by the power supply.
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