Close

Search

Search Menu
Photonics Media Photonics Marketplace Photonics Spectra BioPhotonics EuroPhotonics Vision Spectra Photonics Showcase Photonics ProdSpec Photonics Handbook

Monolithic PIC Platform Combines Efficiency of Light Source, Economy of Scale

Facebook Twitter LinkedIn Email Comments
Photonic chip platforms indium phosphide (InP) and silicon (Si) offer distinct advantages for photonic integrated circuits (PICs). To synergize the capabilities of the two platforms, researchers at Hong Kong University of Science and Technology (HKUST) developed a monolithic InP on silicon-on-insulator (SOI) platform that the researchers believe could chart a course for fully integrated Si-based PICs.

While InP photonics provides optical functionality, the photonic devices and circuits are built on small, expensive InP substrates and produced in low-volume III-V photonic lines. Silicon photonics benefits from mature CMOS manufacturing capabilities — but silicon photonics often must be integrated with III-V lasers to generate light efficiently.

Monolithic integration of III-V light sources on an Si platform through heteroepitaxy could be the answer to fully integrated silicon photonics. For this to be a practical solution, the III-V light sources grown on Si would need to exhibit low-defect density (for reliable device operation); large dimension (for fabrication of electrically driven lasers); and efficient light coupling with Si waveguides.

Led by professor Kei May Lau and researchers Yu Han and Zhao Yan, the HKUST team developed its monolithic InP/SOI platform to meet all three of these critical requirements.

The researchers selectively grew InP submicron wires and large InP membranes on industry-standard (001) SOI wafers using lateral aspect ratio trapping, an approach that resulted in dislocation-free InP on SOI. To develop large-dimension InP membranes, the researchers created deep lateral oxide trenches and changed the growth direction from vertical to lateral.

To synergize the capabilities of InP and Si photonic chip platforms, researchers at Hong Kong University of Science and Technology (HKUST) developed a monolithic InP on silicon-on-insulator (SOI) platform.  The InP/SOI platform could benefit from the well-established processing technologies developed in the III-V heterogeneous integration approach. Courtesy of Zhao Yan, Yu Han, Liying Lin, Ying Xue, Chao Ma, Wai Kit Ng, Kam Sing Wong, and Kei May Lau.
To synergize the capabilities of InP and Si photonic chip platforms, researchers at Hong Kong University of Science and Technology (HKUST) developed a monolithic InP on silicon-on-insulator (SOI) platform. The InP/SOI platform could benefit from the well-established processing technologies developed in the III-V heterogeneous integration approach. Courtesy of Zhao Yan, Yu Han, Liying Lin, Ying Xue, Chao Ma, Wai Kit Ng, Kam Sing Wong, and Kei May Lau.
The epitaxial InP is in-plane and positioned close to the Si device layer to allow an efficient interface for light between the III-V devices and the Si-based waveguides. The InP submicron wire array and large-dimension InP membranes feature an InP-on-insulator that — similar to a silicon-on-insulator — provides a good platform for implementing photonic functionalities.

Using their InP/SOI platform, the researchers demonstrated optically pumped lasers with different cavity designs, including a subwavelength Fabry-Pérot cavity, square cavities, and microdisks. The InP-on-insulator architecture allowed for strong light confinement within the epitaxial InP, and as a result, the researchers obtained a room-temperature and site-controlled laser array from the InP subwavelength wires, and square cavity lasers from as-grown InP crystals. The researchers demonstrated the large-dimension InP membranes’ ability to support top-down processing by fabricating room-temperature microdisk lasers.

The researchers said that, depending on the intended functions of a given device, the InP membranes could serve as templates for the regrowth of a variety of InP-based optoelectronic structures for light emission, modulation, and detection. For example, buried heterostructures, including InGaAs quantum wells and InAs quantum dots, could be formed through selective vertical regrowth. The InP submicron wires could be used as building blocks for subwavelength PICs, and could potentially enable integration with Si-based nanoelectronics.

The InP/SOI platform could benefit from the well-established processing technologies developed in the III-V heterogeneous integration approach, the researchers said.

PICs are the enabling technology for many emerging applications, including high-performance computing, automotive, quantum communications, and optical sensing, and are becoming the backbone of low-power, high-speed datacom/telecom communication systems. The monolithic InP/SOI platform represents an elegant synergy of the conventional InP and Si photonic platforms and supports the trend toward fully integrated PICs.

The research was published in Light: Science & Applications (www.doi.org/10.1038/s41377-021-00636-0).

Photonics Handbook
educationAsia PacificResearch & TechnologyHKUSTHong Kong Applied Science and Technology Research Instituteintegrated photonicsPICssemiconductorsphotonic integrated circuitsPhotonic Integrated Circuits (PIC)indium phosphidesiliconsilicon photonicslight sourcesIII-V CMOSepitaxial depositionmicrolasersnanoelectronicsnanoelectronics applicationsmonolithicmonolithic chipmonolithic CMOS photointegrated circuitmonolithic devicessilicon-on-insulatorsilicon-on-insulator devices

Comments
back to top
Facebook Twitter Instagram LinkedIn YouTube RSS
©2021 Photonics Media, 100 West St., Pittsfield, MA, 01201 USA, [email protected]

Photonics Media, Laurin Publishing
x We deliver – right to your inbox. Subscribe FREE to our newsletters.
We use cookies to improve user experience and analyze our website traffic as stated in our Privacy Policy. By using this website, you agree to the use of cookies unless you have disabled them.