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IP Core

Photonics.com
Feb 2018
FRAMOSRequest Info
 
TAUFKIRCHEN, Germany, Feb. 22, 2018 — The SLVS-EC RX IP Core from Xilinx has been announced by FRAMOS GmbH for easy sensor interfacing with field-programmable gate arrays.

The proprietary module, available with an evaluation board, connects Sony’s latest high-speed SLVS-EC interface with Xilinx FPGAs and enables vision engineers to seamlessly upgrade to Sony’s interface technology and create high-performance vision solutions. The partnership provides the technological basis for future camera developments and embedded vision devices.

Introduced with third-generation Pregius imagers, Sony’s new high-speed interface standard SLVS-EC is one of the future image sensor interface benchmarks, with up to eight lanes, providing 2.3 Gbps each, for three to four times higher bandwidths, higher resolutions or a simplified system design comparing to SubLVDS. The SLVS-EC RX IP Core from Xilinx has been announced by FRAMOS GmbH for easy sensor interfacing with field-programmable gate arrays.

The RX IP Core reduces overhead and complexity by implementing a Sony imager with the SLVS-EC. As on-chip function block connecting the customer’s FPGA logic with the image sensor’s data stream, the IP core receives the interface data, manages the byte-to-pixel conversion for various lane configurations, and thus prepares a highly efficient processing workflow run by the FPGA.


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