IBM, GlobalFoundries, Samsung and equipment suppliers have developed an industry-first process to build silicon nanosheet transistors that will enable 5-nm chips. The details of the process will be presented at the 2017 Symposia on VLSI Technology and Circuits conference in Kyoto, Japan. In less than two years since developing a 7-nm test node chip with 20 billion transistors, scientists have paved the way for 30 billion switches on a fingernail-sized chip. The resulting increase in performance will help accelerate cognitive computing, the Internet of Things and other data-intensive applications delivered in the cloud. The power savings could also mean that the batteries in smartphones and other mobile products could last two to three times longer than today’s devices before needing to be charged. Scientists working as part of the IBM-led Research Alliance at the SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering’s NanoTech Complex achieved the breakthrough by using stacks of silicon nanosheets as the device structure of the transistor instead of the standard FinFET architecture, which is the blueprint for the semiconductor industry up through 7-nm node technology. “For business and society to meet the demands of cognitive and cloud computing in the coming years, advancement in semiconductor technology is essential,” said Arvind Krishna, senior vice president of Hybrid Cloud and director of IBM Research. “That’s why IBM aggressively pursues new and different architectures and materials that push the limits of this industry, and brings them to market in technologies like mainframes and our cognitive systems.” Compared to the leading edge 10-nm technology available in the market, a nanosheet-based 5-nm technology can deliver 40 percent performance enhancement at fixed power or 75 percent power savings at matched performance. This improvement enables a significant boost to meeting the future demands of artificial intelligence systems, virtual reality and mobile devices.