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IP Core for FPGA Interfacing

Photonics.com
Jun 2018
FRAMOS Technologies Inc.Request Info
 
OTTAWA, Ontario, June 11, 2018 — IP Core for FPGA InterfacingFRAMOS Technologies Inc. has announced the SLVS-EC RX IP Core for easy sensor interfacing with Xilinx field-programmable gate arrays (FPGAs).

The proprietary FRAMOS FPGA module, available with an evaluation kit, connects SONY’s latest high-speed SLVS-EC interface with Xilinx FPGAs and enables vision engineers to seamlessly upgrade to Sony’s interface technology of the future and to create high-performance vision solutions. The FRAMOS IP product provides the technological basis for future camera developments and embedded vision devices.

The RX IP Core reduces overhead and complexity implementing a SONY imager with SLVS-EC. As on-chip function block connecting the customer’s FPGA logic with the image sensor’s data stream, the IP Core receives the interface data, manages the byte-to-pixel conversion for various lane configurations, and prepares a highly efficient processing workflow run on the FPGA. The FRAMOS software supports SLVS-EC v1.2 with one, two, four, and eight lanes, configurable by the user and delivering pixels formats from 8- to 14-bit raw data.


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ProductsFramos TechnologiesSLVS-EC RX IP CoreFPGAsensors and detectorsIP CoreAmericas

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