WASHINGTON, Dec. 6 -- Researchers at Agere Systems said they have built the semiconductor industry's smallest transistors that incorporate a novel insulating material aimed at significantly reducing the power used by silicon chips.
The new transistors use hafnium oxide instead of traditional silicon dioxide as the gate insulator -- a thin layer in a transistor that separates the gate, which turns current flow on and off, from the channel through which current flows
In recent years, the semiconductor industry has investigated many so-called high-dielectric constant, or "high-k," materials for use as the gate insulator in future generations of integrated circuits. Hafnium oxide is one of the most promising of these novel materials. As today's silicon dioxide layers are made thinner to support higher switching speeds for enhanced IC performance, they are becoming more prone to letting electrons leak through -- causing increased power consumption and ultimately destroying transistor operation. Gate insulators based on high-k materials can be made thicker to block electron leakage while still enabling high switching speeds.
In a paper presented here at the International Electron Devices Meeting (IEDM), Agere researcher Jack Hergenrother described how he and colleagues Glen Wilk, Tanya Nigam and others incorporated a uniform layer of hafnium oxide (HfO2) with polysilicon gate electrodes in a vertical replacement-gate (VRG) transistor. The VRG transistor is an innovative device structure that the scientists pioneered two years ago while affiliated with Bell Labs, the research and development arm of Lucent Technologies. Agere's VRG devices have gate lengths of 50 nanometers -- about half the size of conventional planar transistors fabricated in today's leading-edge IC processes. The semiconductor industry has identified the VRG transistor as one of the leading novel device structures that might one day supersede the conventional planar transistor, to further extend transistor miniaturization as described by "Moore's law."
"Our VRG structure provides a practical way to achieve very small gate lengths with precise control, but we had to solve the gate insulator leakage issue to maintain the structure's promise for a broad variety of applications in upcoming IC generations," said Hergenrother. "The challenge was that the device's geometry makes it inherently more difficult to incorporate high-k gate insulators. Now we've successfully introduced a uniform layer of hafnium oxide using a manufacturable deposition technique, and the devices show greatly reduced leakage -- at least 100,000 times less than found with silicon dioxide."
Atomic layer technique
The deposition technique that Agere's researchers used is known as atomic layer deposition (ALD). The depositions were performed by engineers at ASM America, a subsidiary of ASM International and a leading supplier of semiconductor wafer processing equipment, using ASM's Polygon gate stack cluster tool to provide the ALD process. ALD provides outstanding conformality -- meaning that the deposited layer has the same thickness on all surfaces even in deep trenches or narrow cavities -- a key requirement for the successful incorporation of hafnium oxide in the VRG structure.
"The excellent conformality of ALD can be illustrated by considering how water condenses on an object such as a drinking glass," said Hergenrother. "If you chill a glass and then move it to a humid environment, water will initially condense evenly over all of the outside and inside surfaces. Other less conformal deposition techniques are like trying to wet the glass using a spray bottle -- surfaces facing the sprayer get soaked while other surfaces remain dry."
Agere's transistors are among the industry's first with hafnium oxide deposited by ALD, widely considered a highly viable deposition technique for manufacturing when high-k materials become commercially attractive. Until now, the technique's suitability for use with novel transistor structures such as the VRG had not been demonstrated. Since the VRG transistor provides a very challenging geometry for gate insulator deposition, Agere's researchers said they believe ALD should be well-suited to any conventional or novel silicon-based transistor structure.
Agere's researchers achieved these low gate leakage currents with a polycrystalline high-k gate insulator, in which atoms are aligned in a more orderly fashion than in amorphous insulators such as silicon dioxide. Polycrystalline gate insulators are generally more prone to letting electrons leak through, but their use provides greater flexibility in the overall semiconductor fabrication process. According to Hergenrother, these results suggest that with hafnium oxide, an amorphous dielectric may not be necessary to meet gate insulator leakage requirements, although reliability and yield issues require further investigation.