Camera Chip Promises Higher-Quality Images at Lower Power
Scientists at the University of Rochester in New York have developed two technologies that may enable the design of CMOS image sensors with a higher performance than today’s chips and using a fraction of the power.
Mark F. Bocko and Zeljko Ignjatovic of the university’s department of electrical and computer engineering have found that they can incorporate an oversampling sigma-delta modulator at each pixel in the sensor using only three transistors at each pixel site to perform on-pixel analog-to-digital conversion. The modulator thus offers a higher fill factor than previous sigma-delta pixel designs. A prototype 128 × 128-pixel device demonstrated a linear dynamic range of 100 dB and power consumption of 0.88 nW per pixel at 30 frames per second.
They also have proposed using a nonuniform tiling of pixels in the image plane to simplify the computation required to compress images, which would further reduce power consumption. The pixels would be positioned at the points in the image plane where the cosine functions used in the discrete cosine transform step of jpeg compression have a value of 1, effectively eliminating the multiplication step.
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