Close

Search

Search Menu
Photonics Media Photonics Buyers' Guide Photonics EDU Photonics Spectra BioPhotonics EuroPhotonics Industrial Photonics Photonics Showcase Photonics ProdSpec Photonics Handbook
More News
share
Email Facebook Twitter Google+ LinkedIn Comments

Light Is the Ultimate Medium for High-Speed Communications

EuroPhotonics
Mar 2017
Thanks to innovations with heterogeneous material integration and multiphotonic layer stacking, silicon photonics will drive optical solutions to high volumes and low costs.

Christophe Kopp, Ségolène Olivier and Stéphane Bernabé, CEA-LETI

Silicon photonics is widely considered a key enabling technology for further development of optical interconnect solutions needed to address growing traffic on the internet. From the first submarine optical cable to the fiber-to-home deployment to the proliferation of data centers, light has served as the ultimate medium for high-speed optical communications for more than 20 years. Compared with copper wiring, at low energy per high-speed channels, optical interconnect can work over long and short distances with low latency leading to high-speed, end-to-end network paths, as well as new architectures with a unified switched photonic network. For this reason, optical links are being implemented at many internet network levels into modules, including server, switch, network-attached storage, clients and others.

In this context, silicon photonics is a relevant technology to drive optical solutions to high volumes and low costs. Indeed, several platforms have been developed as photonic integrated circuit (PIC) technologies — glass, plastic, silica-on-silicon, indium phosphide, lithium niobate and silicon-on-insulator (SOI). These platforms exhibit a rather uneven integration capability level, with respect to the optical mode confinement level and the possibility to implement passive and/or active functions. In this quest for higher integration, silicon photonics on an SOI platform provides a wide panel of benefits.

Optoelectronic integration

Thanks to the high index contrast between silicon and oxide, small footprint circuits can be designed with submicron-mode field diameter and few-micron waveguide bend radius. Moreover, silicon material is amenable to optoelectronic integration, as it is both semiconducting and transparent in the telecom wavelength domain. It is then highly scalable to increase the bit rate per channel on the same chip by implementing wavelength multiplexing and advanced modulation formats. In addition, the use of microelectronic CMOS fabrication lines allows low-cost mass production. For instance, fabrication on 200-mm- or 300-mm-diameter wafers enables high-volume performance measurement with wafer-level automated testers (Figure 1).

Wafer-level automated testing of a photonic integrated circuit.


Figure 1. Wafer-level automated testing of a photonic integrated circuit. Courtesy of Leti.


In order to solve electrical interconnect limits in data centers and supercomputers, silicon photonics has attracted increasing investments. This presents a unique opportunity to address the requirements of next-generation optical interconnects in small form factor modules, from long-haul transmissions to data center short reaches and high-performance computing. There are many advantages to PIC-based modules compared with legacy technologies (VCSELs or InP laser modules). Among them, silicon photonics enables integration of a high number of optical functions, such as laser source, modulator, wavelength-management devices and photodiodes, on a single chip. This allows use of complex photonic circuitry to transmit and detect complex modulation formats, including polarization diversity multiplexing quadrature phase-shift keying (PDM-QPSK) for coherent transmission.

Metro networks and links between data centers

An advanced modulation format, using both the amplitude and phase of the light wave to code the binary signal, is likely to be used in metro networks and inter-data centers. This allows data rates of 100 Gbps per optical channel per wavelength with hardware bandwidth limited to 25 GHz, as well as an easier assembly process because existing technologies combine discrete parts. Such silicon photonics-based coherent transceivers are already commercialized by companies including Acacia Communications.

Another advantage of silicon photonics modules is the prospect of managing links below the kilometric range to connect switches in data centers, possibly using wavelength multiplexing. This extends the aggregated bandwidth and range of today’s optical links in data centers, which rely on VCSEL-based transmitters using intrinsically limited multimode fiber as an optical medium. As a result, several commercial products for data center applications have recently emerged, with a data rate of 100 Gbps per module such as 100G-LR4 CPAK (Cisco), 100G QSFP28 (Mellanox) and 100G CWDM4 QSFP28 (Intel). Due to the scalability potential of silicon photonics, terabit-class modules are expected in the near future, following the roadmap for internet switches, with bandwidth densities as low as 40 Gbps/cm2 and reduced power consumption.

To achieve these targets, several main challenges have been addressed: circuit integration, module integration, and fiber and laser integration. Circuit integration can be efficiently performed with the related design tools if integrated fabrication flows are available at high maturity level. Today, several design kits are available on various CAD tools. These design kits are proposed through multi-project wafers, which integrate on the same wafers as the designs from various teams (R&D firms and researchers) in order to share the fabrication cost to produce designs in low quantities.

Module integration with ASICs and PICs

Module integration of silicon photonic circuits into high data rate transceiver modules is conveniently addressed using advanced packaging technologies such as flip-chip stacking of driving electronics (ASICs) on PICs, using copper micropillars (Figure 2).

A 100-Gbps receiver with a four-electrical-channel TIA stacked onto a four optical channel photonic integrated circuit.
Figure 2.
A 100-Gbps receiver with a four-electrical-channel TIA stacked onto a four optical channel photonic integrated circuit. Courtesy of Leti.

Thanks to low parasitics and reduced signal path between ASICs and PICs, this approach is particularly suited for 56 Gbps (and beyond) data rate applications. In addition, the chip-to-chip integration strategy uses an established high-yield assembly process based on the known good die (KGD) approach.

To increase even further the aggregated bandwidth of the modules, while keeping the form factor as small as possible, 3D integration approaches will also be required in the future. A short-term approach is the integration of through-silicon vias (TSVs), which are vertical electrical connections passing completely through a silicon wafer or die, in the PIC. By achieving greater space efficiencies and higher interconnect densities than wire bonding and flip-chip stacking, TSVs are mandatory to develop high-speed optical interposers at smaller geometries with higher input/output. Such integration will be a key enabler for next-generation devices, addressing terabit-scale modules in data centers, as well as optical network-on-chip in many-core processor interconnect architectures for high-performance computing (Figure 3).

An example of Ta high-speed optical network on chip interposer for multiple core-processor interconnect architectures.
Figure 3.
An example of Ta high-speed optical network on chip interposer for multiple core-processor interconnect architectures. Courtesy of Leti.

A long-term approach is 3D photonic circuitry using multiple layers of optical waveguides on the same chip (Figure 4). With this method, at least two silicon photonic circuits will operate together.

New options for designers

The silicon waveguide layers are close enough (i.e., 100 nm) to deal with efficient optical coupling. This integration scheme will offer a new degree of freedom to designers, both to improve the performance of existing components and to develop new functions. An early example of this approach involves the introduction of a silicon nitride optical layer, the refractive index of which is much less sensitive to temperature than silicon. This property can be exploited to build nearly thermally insensitive wavelength multiplexers (MUX), which are required for low-cost coarse wavelength division multiplexing (CWDM) applications where the photonic integrated circuit will remain uncooled. In such cases, thermally insensitive MUX are required to cope with ±10-nm laser wavelength variations for each channel.



Figure 4. 3D photonic circuitry using multiple layers of optical waveguides.Courtesy of Leti.

Silicon photonics offers then a very attractive scalable platform to fulfill the demands of next-generation telecom and datacom interconnects. However, another big challenge is still the integration of laser sources. Until now, the laser source has remained separated from the rest of the chip, leading to high-cost packaging complexity and unavoidable coupling losses to the rest of the circuit. However, one promising short- and medium-term solution exists in the heterogeneous integration of III-V semiconductors with silicon through direct-bonding techniques. Here, unstructured InP wafers or dies are bonded with relaxed alignment tolerances, and epitaxial layers are face down on a silicon-on-insulator wafer structured with optical waveguide circuits such as passives, modulators and photodetectors. The InP growth substrate is removed and the III-V epitaxial film is processed.

This approach exploits the highly efficient light-emission properties of III-V semiconductor materials, as well as the compact and low-loss photonic circuits on silicon. Light is generated in the III-V material and couples with the silicon circuitry thanks to the use of adiabatic tapers (Figure 5).

his illustration shows a laser source by heterogeneous integration of III-V gain medium on a photonic integrated circuit.
Figure 5.
This illustration shows a laser source by heterogeneous integration of III-V gain medium on a photonic integrated circuit. Courtesy of Leti.

Advantages of fabrication on silicon

All the elements of the laser cavities — except the gain medium — are fabricated in the silicon, on which higher performance can be achieved thanks to the higher maturity of silicon fabrication processes, namely the cavity mirrors, such as Bragg mirrors, and additional filtering elements. Vertical fiber couplers are also fabricated in silicon for light output of the lasers.

A key achievement has been the integration of lasers on silicon for various communications applications. Tunable lasers over a wide wavelength range of 40 nm, with a power level close to that of bulk InP lasers, have been developed by III-V Lab and Leti for metro networks using dense wavelength division multiplexing (DWDM). Direct modulation of these tunable lasers at 10 and 25 Gbps has been demonstrated for use in access networks. Distributed feedback lasers, which feature a robust single-mode behavior, have also been developed successfully for data center applications, where low cost per bit-per-second is key.

Such hybrid III-V-on-silicon integration also offers new options for modulation and detection. Other active devices such as electro-absorption modulators, photodiodes and light amplifiers can also be realized by engineering of the III-V heterostructure. In this perspective, one of the attractive features of heterogeneous integration using dies is the wide choice of gain materials, allowing separate optimization of lasers, III-V electro-absorption modulators and photodiodes to build high-performance, high-speed and low-power consumption transmitter circuits. Aurrion (now Juniper Networks), for instance, has developed a four-wavelength transmitter at a speed of 28 Gbps per channel, including lasers and electro-absorption modulators driven by co-integrated CMOS circuits. Beyond III-V materials, this heterogeneous integration technology opens the door to implementation of various materials on PICs in order to address new functions, such as nonlinear optics.

Public-private partnerships

Based on this level of maturity of silicon photonics technology, new application areas are targeted for optical communications and beyond. Next-generation technologies and applications are in development in R&D public-private partnership initiatives such as Japan’s PETRA, France’s IRT NANOELEC and AIM Photonics in the U.S. For optical interconnects, the short- and mid-term goals are focused on the data center applications with migration of the optical transceivers closer to the electronics, from front panel modules to mid-board optics raising compact packaging challenges.

The ultimate integration level goes a step further by considering optical networking at the chip level with 3D integration of photonics and electronics for many core processor architectures. Beyond optical interconnect applications, new areas for exploration include sensors for IoT, imagers for augmented reality, and biophotonics for health care.

This evolution of the applications of silicon photonics requires both the integration of new functions with new materials and an increase in the number of optical layers.

Meet the authors

Christophe Kopp, Ph.D., is head of the Leti Silicon Photonics Laboratory; email: Christophe.Kopp@Cea.Fr.

Ségolène Olivier, Ph.D., is a Leti research group leader, dealing with heterogeneous integration for advanced photonic components; email: Segolene.Olivier@Cea.Fr.

Stéphane Bernabé is a research group leader for IRT Nanoelec, focusing on high-speed optical interconnects; email: Stephane.Bernabe@Cea.Fr.

GLOSSARY
chip
1. A localized fracture at the end of a cleaved optical fiber or on a glass surface. 2. An integrated circuit.
CEATunable LasersLETIoptical interconnectsiliconphotonic integrated circuitsPICsilicasilicon-on-insulatorSOICMOSoxideWafersVCSELEuropeInPlaserssensorswavelengthphotodiodeschipPDM-QPSKpolarization diversity multiplexing quadrature phase-shift keyingInternetCADR&Dfiber opticsmicropillarsASICknown good dieKGD3Doptical network-on-chipoNoCmultiplexersMUXcoarse wavelength division multiplexingCWDMdatacomtelecomepitaxial layerssemiconductoradiabatic tapersBragg mirrorfiber couplersdense wavelength division multiplexingDWDMIII-V-on-siliconnon-linear opticsChristophe KoppSégolène OlivierStéphane BernabeIRT NanoelecLeti Silicon Photonics LaboratoryFeatures

Comments
Terms & Conditions Privacy Policy About Us Contact Us
back to top

Facebook Twitter Instagram LinkedIn YouTube RSS
©2017 Photonics Media
x Subscribe to EuroPhotonics magazine - FREE!